Testing and Diagnosing Dynamic Reconfigurable FPGA

Dynamic Partial Reconfigurable FPGA Framework For Agent Systems

Dynamic Partial Reconfigurable (DPR) FPGAs enable software such as threads and agents to be executed directly in hardware. However, they were utilized as hardware extensions of software to execute individual threads or threads encapsulated in an agent. Thus, it was necessary for these systems to be administered by a CPU and did not take full advantage of the concurrency features that FPGAs prov...

Testing Interconnects of Dynamic Reconfigurable FPGAs

Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice for fast prototyping and for products whose time to market is relatively short. Testing FPGAs before programming them is thus becoming a major concern to the manufacturers as well as the users. In this paper we propose a universal test for the interconnects of typical dynamic reconfigurable FPGAs. The proposed test config...

Design Methodologies for Dynamic Reconfigurable Multi - Fpga Systems

FP3 - A Dynamically Reconfigurable FPGA

Fig. 3 Logic Element (LE) of FP3 including the proposed TCM AbstractThis paper studies issues concerning dynamically reconfigurable FPGA (DRFPGA). It reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. The FP3 employs a new shift register-type temporal interconnect to reduce operation delay. Designed and fabricated in 0.35um 2P3M CMOS technology, F...

Reconfigurable cache Implementation on FPGA

Cache memory is a common structure in computer system and has an important role in microprocessor performance. The design of a cache is an optimization problem that is mainly related with the maximization of the hit ratio and the minimization of the access time. Some aspects related with the cache performance are the cache size, associativity, number of words per block and latency. In this pape...